The present invention relates to a method of manufacturing a semiconductor device incorporating a capacitor element and the like and, more particularly, to a method of manufacturing a semiconductor device using an HSG (Hemi-Spherical-Grain) technique.
In the manufacture of dynamic random access memories (DRAMs) and the like, a higher integration degree has conventionally been required. To meet this requirement, an area necessary for each memory cell in the DRAM is greatly reduced. For example, in a 1- or 4-Mbit DRAM, a design rule using a minimum design width of 0.8 .mu.m is employed; in a 16-Mbit DRAM, a design rule using a minimum design width of 0.6 .mu.m is employed.
While the memory capacity increases in this manner, the semiconductor chip size cannot be increased in terms of high manufacturing efficiency and low cost. How to reduce a memory cell area is therefore an important theme in such semiconductor techniques.
A reduction in memory cell area results in a small charge storage amount. For this reason, it is becoming difficult to ensure a necessary charge amount of the memory cell along with an increase in integration degree of the memory cell. To solve this problem, memory cells having trench capacitors and stacked capacitors have conventionally been proposed and used in practical applications.
Of these memory cells, the memory cell having a stacked capacitor is advantageous in that its structure has high resistance to software errors and does not damage an Si substrate, compared to the structure of the memory cell having a trench capacitor. The memory cell structure having a stacked capacitor is expected as a next-generation memory cell structure.
The memory cell structure having a stacked capacitor is formed by an HSG technique in which a plurality of convexities are formed on the surface of a capacitor element to increase the charge storage amount.
The stacked capacitor is made up of a lower electrode, a capacitor insulating film, and an upper electrode. The lower electrode is electrically connected through a contact hole formed in an interlevel insulating film to a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) formed in a semiconductor substrate. In this case, many hemispherical grains are formed on the surface of a storage electrode operating as the lower electrode of the capacitor to substantially increase the surface area of the storage electrode and obtain a large capacitance.
Several types of HSG technique are available. Of these techniques, so-called nucleation of forming nuclei by irradiation of SiH.sub.4 or the like on an amorphous silicon surface and forming convexities by annealing is proposed.
FIGS. 4A to 4C show the steps in manufacturing a capacitor element by a conventional nucleation method. As shown in FIG. 4A, after a capacitor contact hole 2a is formed in an Si oxide film 2 made of BPSG (BoroPhosphoSilicate Glass) or the like on an Si substrate 1, doped amorphous silicon containing phosphorus at a concentration of 1E20 to 1E21 cm.sup.-3 is grown and formed into a stack shape (to be referred to as an amorphous silicon stack hereinafter) 3 by lithography and etching.
As shown in FIG. 4B, after the amorphous silicon stack 3 is cleaned to remove a native oxide film formed on its surface, the obtained structure is heated to 570.degree. C. in an HSG processing apparatus (not shown) and irradiated with disilane (Si.sub.2 H.sub.6) at 1 mTorr for 40 sec to form nuclei 4 on the surface of the amorphous silicon stack 3.
As shown in FIG. 4C, the obtained structure is annealed in a high vacuum at 570.degree. C. for 2 min upon the irradiation of disilane, thereby forming hemispherical or mushroom-like HSG grains 7 on the surface of the amorphous silicon stack 3. By the annealing, a crystallized layer 6 is internally grown from the surface of the amorphous silicon stack 3, whereas a crystallized layer 5 is grown from the interface between the Si oxide film 2 and the amorphous silicon stack 3.
If this annealing is continuously performed, the crystallized layer 5 may reach the crystallized layer 6 before the HSG grains 7 completely grow. Once the crystallized layer 5 reaches the crystallized layer 6, subsequent HSG processing stops, and an ungrown portion 10 of the HSG grain 7 may be formed, as shown in FIG. 4C.
For this reason, a method of suppressing the growth of the crystallized layer 5 by forming an undoped amorphous silicon layer at the interface between the amorphous silicon stack 3 and the Si oxide film 2 has conventionally been proposed. FIGS. 5A to 5C show the steps in manufacturing a capacitor element in which an undoped amorphous silicon layer is formed at the interface.
As shown in FIG. 5A, after a capacitor contact hole 12a is formed in an Si oxide film 12 made of BPSG or the like on an Si substrate 11, an undoped amorphous silicon layer 18 is grown. Doped amorphous silicon containing phosphorus at a concentration of 1E20 to 1E21 cm.sup.-3 is grown on the undoped amorphous silicon layer 18 and formed into an amorphous silicon stack 13 by lithography and etching.
As shown in FIG. 5B, the amorphous silicon stack 13 is cleaned to remove a native oxide film formed on its surface. Then, the obtained structure is heated to 570.degree. C. in an HSG processing apparatus (not shown) and irradiated with disilane (Si.sub.2 H.sub.6) at 1 mTorr for 40 sec to form nuclei 14 on the surface of the amorphous silicon stack 13.
As shown in FIG. 5C, the obtained structure is annealed in a high vacuum at 570.degree. C. for 2 min upon the irradiation of disilane, thereby forming hemispherical or mushroom-like HSG grains 17 on the surface of the amorphous silicon stack 13. By the annealing, a crystallized layer 16 is internally grown from the surface of the amorphous silicon stack 13, whereas a crystallized layer 15 is grown from the interface between the Si oxide film 12 and the amorphous silicon stack 13, similar to the steps in FIGS. 4A to 4C.
Since the undoped amorphous silicon layer 18 is formed at the interface between the Si oxide film 12 and the amorphous silicon stack 13, the growth rate of the crystallized layer 15 is lower than that in the steps of FIGS. 4A to 4C. Therefore, the crystallized layer 15 does not reach the crystallized layer 16 before completion of the growth of the HSG grains 17.
According to the above conventional example, the growth of the crystallized layer can be suppressed by forming the undoped amorphous silicon layer 18. However, forming the undoped amorphous silicon layer 18 undesirably increases the contact resistance between the amorphous silicon stack 13 and the Si substrate 11.